ANKASYS Verilog-2D is a 2-Day Verilog For Design and Verification Training, which has all the required tools to get you started with your first design with Verilog language.

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ANKASYS Verilog-2D Details

  • DAY 1

    • Introduction to Verilog language and its history up to the latest SystemVerilog standard
    • Verilog-VHDL comparison
    • Continuous and procedural statements
    • Data types and their usage
    • Blocking and non-blocking assignments

    DAY 2

    • User/System Tasks and functions
    • File I/O and PLI
    • Combinatorial and sequential logic design
    • Synthesis and synthesizable RTL coding styles
    • User Defined Primitives (UDP)
    • Timing delays and timing checks
    • Building a Verilog testbench
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