ASIC Design

ANKASYS provides turnkey ASIC design solutions from spec to final GDS.

ASIC Verification

ANKASYS provides verification services by using
state of the art verification languages and methodologies.

FPGA Design and Verification

ANKASYS provides FPGA design and verification services
for FPGAs from different providers and families.


ANKASYS is delivering ASIC and FPGA design and verification trainings.

Flexible Consultancy

ANKASYS provides flexible consultancy services
for the complete ASIC and FPGA design flows.

About Us

From Dream to Reality

ANKASYS was born after winning a competition with its so-called "GEZGIN" project organized by The Scientific and Technological Research Council of Turkey in 2012.GEZGIN was one of the 95 successful projects out of roughly 1200 submitted projects.

ANKASYS was founded with a passion of being the first Turkish start-up company working in semiconductor area in the complete design flow from specification to the final product.


We are a microelectronic design and verification company, founded in 2013 in Istanbul, Turkey. We opened in January 2016 our European branch in Wädenswil, Switzerland. We provide advanced design and verification services to our customers from specification to final GDSII for tapeout. We have more than a decade of ASIC/FPGA design experience at advanced technology nodes from 90nm down to 28nm and in applications where high reliability is key requirement (such as automotive), or where low power design is needed (for mobile or portable electronics).

Our services covers but not limited to frontend design activities such as RTL development in all three major languages (VHDL, Verilog, SystemVerilog), advanced verification using state of the art techniques (metric driven constrained random verification and UVM), and RTL2GDSII design activities such as DFT, synthesis (FPGA/ASIC), physical implementation (place and route, STA, DRC, LVS and final signoff), packaging and post silicon validation. We have designed board level systems with low-level firmware development.

ANKASYS also provides training services. Recent trainings are "3-day SystemVerilog for Verification" and "4-day Universal Verification Methodology (UVM)".

We develop SystemVerilog based, UVM compliant verification IPs. Recently we released ANKASYS SPI UVCS, which covers not only the verification IP (VIP) itself but also the surrounding integration and customization services.

We are targeting to develop our own software solutions as well and recently announced STDF (Standard Test DATA Format) analysis tool, the ANKASYS DAP (Data Analysis Platform). ANKASYS DAP helps test and quality engineers analyze the ATE generated data in a user-friendly and efficient way by providing direct access to plain text, csv or SDFT formatted files without requiring a database or a third party tool. We are working hard to achieve our goals and deliver high quality services and products to our customers.

For more information please reach us at, or

Focus Areas

  • ASIC Design & Verification
  • ASIC Physical Design (RTL2GDS)
  • FPGA Design & Verification
  • Embedded System Design
  • Board-Level System Design
  • Training
  • Consultancy






Board-level System Design

Previous Experience

  • RTL Design

    VHDL, Verilog, System Verilog RTL coding

  • Verification

    Directed and Constrained Random Verification by using C/C++, System Verilog and UVM

  • Synthesis

    RTL to Netlist flow with constraint development

  • DFT

    Design for testability concept development and implementation

  • Physical Implementation

    RTL2GDS flow from 1.8um down to 28nm (Floorplanning, Placement, Clock Tree Synthesis, Routing)

  • Signoff

    Extraction, Physical Verification (DRC/LVS), Constraint Development and Static Timing Analysis (STA), Formal Equivalance Checks, Power Analysis, IR Drop Analysis

  • Post Silicon Validation

    Testing on ATE and lab validation.