ANKASYS SPI UVCS(Universal Verification Component and Services) is a unique VIP (Verificatin IP) product, which combines a universial verification component with its corresponding integration and on-demand development service.

  • Easy integration and user interface.
  • All four SPI modes are supported.
  • Multi slave configuration with unlimited number of slaves
  • Automatic driver and monitor thread termination support via a single enabling bit.
  • Supports both single and burst transfers
  • Ready-to-use Systemverilog Assertion(SVA) based protocol chechers.
  • Random and selectable pre/post delay injections.
  • Pre-defined Systemverilog covergroups.


  • 1.Systemverilog Implementation

    The implementation is done in SystemVerilog with an easy to use coding style.

  • 2.UVM Compliant

    The complete VIP component hierarchy and test codes are driven from the standart UVM library.Example UVM sequences and test codes are provided as part of the ANKASYS SPI Verification IP.

  • 3.SPI Protocol Supports

    Following list shows some features of the ANKASYS SPI UVCS. for more details please have a look at the Brochure.