ANKASYS Verilog-2D
ANKASYS Verilog-2D Details
Day 1
- Introduction to Verilog language and its history up to the latest SystemVerilog standard
- Verilog-VHDL comparison
- Continuous and procedural statements
- Data types and their usage
- Blocking and non-blocking assignments
Day 2
- User/System Tasks and functions
- File I/O and PLI
- Combinatorial and sequential logic design
- Synthesis and synthesizable RTL coding styles
- User Defined Primitives (UDP)
- Timing delays and timing checks
- Building a Verilog testbench