Successful tapeouts
Block and top-level silicon implementation across multiple process technologies and application domains.
TWO PILLARS · ONE MICROELECTRONICS TEAM
Silicon engineering.GNSS technology.
Specialist ASIC/FPGA design and verification alongside a complete multi-constellation receiver platform — both built on deep digital hardware expertise.
ANKASYS GNSS RECEIVER
ASIC · FPGA · VERIFICATION
WHY ANKASYS
Evidence from delivered engineering.
A compact engineering team with hands-on scope across silicon implementation, verification, safety-critical workflows and reusable IP.
End-to-end engineering
Architecture, RTL, verification, synthesis, DFT, physical implementation, sign-off and post-silicon support.
Safety-critical verification
Structured verification and assurance work across avionics, automotive, industrial and energy programs.
Reusable & licensable IP
GNSS correlator technology, protocol VIP and reusable UVM methodology alongside engineering delivery.
CHOOSE YOUR PATH
Engineering delivery or receiver technology.
Two commercial paths, one microelectronics team. Start with specialist engineering support or integrate ANKASYS GNSS technology into your platform.
Take complex digital hardware from architecture to sign-off.
Focused support or end-to-end ownership across ASIC/SoC, FPGA, SystemVerilog/UVM verification, physical implementation and safety-critical programs.
Explore engineering servicesBuild precise positioning around a proven GNSS platform.
Six constellations across L1, L2 and L5 with RTK, EGNOS/SBAS, Galileo OSNMA and HAS, dead reckoning and reusable correlator IP for FPGA or ASIC.
GPS · Galileo · BeiDouGLONASS · QZSS · NavICL1 · L2 · L5 · RTK
SELECTED PROJECT EVIDENCE
Engineering challenges turned into delivered outcomes.
Three anonymized examples showing the engineering challenge, ANKASYS scope and resulting technical evidence.
RTL → GDS01 · SILICON IMPLEMENTATION
RISC-V-based SoC implementation
Challenge. Move a complex processor-based SoC from digital design into a manufacturable implementation.
Scope & outcome. Synthesis, DFT, physical implementation, timing closure and sign-off support delivered through the RTL-to-GDS flow.
RTL · Synthesis · DFT · Sign-offExplore ASIC / SoC engineering →REQUIREMENTSUVM + VIPCOVERAGE CLOSURE
MEASURABLE VERIFICATIONSVA · REGRESSION · FPGA/ASIC COVERAGE02 · DESIGN VERIFICATION
Industrial mixed-signal measurement IC
Challenge. Verify control logic and analog-data paths against traceable system requirements.
Scope & outcome. A reusable UVM environment, custom VIP, automated regressions and combined FPGA/ASIC coverage analysis created measurable closure evidence.
SystemVerilog · UVM · SVA · CoverageExplore verification engineering →
REAL-WORLD GNSS VALIDATION03 · GNSS RECEIVER
Explore GNSS receiver technology →
Multi-band positioning and PPS validation
Challenge. Validate receiver timing and positioning performance outside synthetic-signal testing.
Scope & outcome. L1+L5 receiver hardware, digital processing and PPS were measured with real-world signals and laboratory references.
0.390 mBest horizontal RMS
0.479 mBest vertical RMS
45-minute L1+L5 PVT test, without external assistance: no RTK, HAS or EGNOS/SBAS.
A simultaneous bench comparison against a best-in-class commercial GNSS timing receiver showed lower observed PPS jitter across three stability metrics.
- Centered RMS
- 3.68 ns vs 4.32 ns · 14.9% lower
- Detrended RMS
- 3.54 ns vs 4.11 ns · 13.9% lower
- Max. deviation
- 11.15 ns vs 12.28 ns
- Peak-to-peak
- 22.29 ns vs 22.19 ns
MORE FROM ANKASYS
Company life, training and updates — when you need the detail.
SELECTED ENGINEERING CHALLENGES
Representative engineering problems we have solved.
Examples are described by the engineering problem and ANKASYS scope. Customer-owned product imagery and confidential implementation details are omitted where appropriate.
Complex RTL-to-GDSII ownership
Block and top-level physical implementation across low-power, mixed-signal and high-performance digital designs, including DFT, timing closure and sign-off.
50+ successful tapeoutsHigh-density processor systems
Silicon implementation experience includes processor-centric SoCs and a neural-network accelerator integrating 128 RISC-V cores.
Multi-core · PPA · physical implementationMixed-signal IC verification
Requirements-based, coverage-driven UVM verification with SVA, scoreboards, register models, automation and customer-environment integration.
SystemVerilog · UVM · SVACertification-oriented avionics verification
FPGA/CPLD verification, traceability and lifecycle support aligned with DO-254 across multiple Design Assurance Levels.
DO-254 · DAL A/B/C/D experienceProcessor SoC bring-up on FPGA
LEON3-based SoC implementation, custom toolchain work, Linux and firmware bring-up, peripheral integration and cross-family PPA exploration.
FPGA · Linux · firmware · peripheralsReusable receiver technology
Multi-constellation correlator IP for FPGA and ASIC implementation, validated with synthetic and real-world signals and delivered to customers.
Correlator IP · FPGA · ASIC · PPS
ENGINEERING IN THE COMMUNITY
Sharing engineering practice beyond project delivery.
ANKASYS has taken part in technical events, university programs and industry conferences alongside commercial engineering work. This archive image is from an engineering presentation at İTÜ in 2018.
See Life at ANKASYS →SIX CONSTELLATIONS · L1 + L2 + L5 · RTK
One receiver platform, from RF to resilient positioning.
ANKASYS develops a multi-band receiver platform supporting GPS, Galileo, BeiDou, GLONASS, QZSS and NavIC across L1, L2 and L5, with RTK, EGNOS SBAS, Galileo OSNMA and HAS, plus dead-reckoning capability.
GPSGalileoBeiDouGLONASSQZSSNavICL1 + L2 + L5RTKEGNOS / SBASOSNMAHASDead reckoningLow-jitter PPS
Receiver engineering + licensable correlator IP.
The platform joins ANKASYS RF hardware, flexible sampling and IF support, reusable correlator technology and receiver-level validation. The digital architecture maps across FPGA families without vendor-specific resources and provides a direct path to ASIC integration.
ANKASYSGNSS CORRELATOR IPReusable digital baseband technology
Digitized I/QCorrelatorTracking / PPS
01No 3rd-party CPU/DSP IP license required
02Validated with synthetic and real-world signals
03Delivered to customers
04Customizable for target requirements
SELECTED ORGANIZATIONS ANKASYS HAS SERVED
Engineering relationships across global technology programs.
A selected set from ANKASYS project history.
RRenesas
IIntel
IFInfineon
iimec
QQorvo
E+HEndress+Hauser
SSensirion
TTÜBİTAK
AASELSAN
TTeradyne
SSemtech
IDTIDT
CAPABILITIES
Engineering depth from RTL to silicon.
Architecture, RTL, FPGA implementation, verification, DFT, physical design and sign-off — delivered as focused engineering support or a broader development scope.
01
ASIC / SoC Design
Architecture, RTL design, synthesis, DFT, physical implementation and sign-off oriented RTL-to-GDS engineering.
Explore → 02FPGA Design
RTL design, timing-driven implementation, prototyping and hardware/software integration for modern FPGA and SoC-FPGA platforms.
Explore → 03Design Verification
SystemVerilog and UVM verification with assertions, coverage, reusable environments, protocol VIP and automation.
Explore → 04Physical Design
Synthesis, STA, DFT, placement & routing, power analysis, IR drop, DRC/LVS, equivalence and sign-off flow expertise.
Explore → 05RISC-V & Processor Systems
Processor/SoC implementation and verification experience, including ASIC design and RTL-to-GDS support for RISC-V based systems.
Explore → 06Safety-Critical Engineering
DO-254 focused design and verification methodology, structured evidence generation and certification-oriented engineering support.
Explore →IP & PRODUCTS
Engineering assets built for reuse.
Selected ANKASYS know-how is packaged as reusable IP, verification components and methodology that can be licensed, integrated and customized.
LICENSABLE GNSS IP
GNSS Correlator IP
Multi-constellation correlator IP for hardware-based GNSS receivers, supporting flexible sampling/IF configurations and FPGA or ASIC integration.
VERIFICATION PLATFORM
UVM-Xpress
A productive UVM-based verification environment built around reusable infrastructure, debugging, reporting and logging mechanisms.
Product page →Verification
VERIFICATION IP
Protocol VIP Library
Reusable verification components spanning common serial, on-chip, avionics, space and digital interfaces.
Base VIPSPIUARTI²CJTAGSpaceWireARINC708AAXI Lite / Stream / FullAvalonDVILVDSBT656I²SQSPIRDMA
COMPANY
Built around engineering delivery.
Explore the people, delivered work and engineering roles behind ANKASYS.
Management
Meet ANKASYS co-founders and engineering leadership.
Meet the management team →Experience
Selected engineering programs, customers and project history.
Explore experience →Careers
Join an engineering team working across silicon, FPGA, verification and GNSS.
View careers →ABOUT ANKASYS
Microelectronics engineers working on hard hardware problems.
ANKASYS was founded by semiconductor design engineers. The team works across ASIC/SoC, FPGA, verification, reusable IP and system integration, with experience in commercial products, high-reliability programs and international R&D.
Design + VerificationOne engineering organization spanning RTL, UVM, implementation and sign-off.
Reusable IPUVM-Xpress, protocol VIP and GNSS correlator technology.
System CapabilityFPGA platforms, embedded integration and GNSS receiver systems. Explore →
Knowledge TransferTechnical training grounded in real project delivery.
Join the engineering team.
Current roles include functional verification, ASIC/SoC physical implementation, senior verification and GNSS design.
SELECTED NEWS
A few milestones worth reading.
Editorially selected engineering and company milestones. The complete chronological archive remains available on the News page.
ANKASYS at the ESA/JRC International Summerschool on GNSS 2026
ANKASYS participated in the 17th ESA/JRC International Summerschool on GNSS, joining an international community focused on satellite navigation and GNSS technologies.
Read story →
ANKASYS Provided ASIC Design & Verification Services for the RISC-V Based ÇAKIL Microprocessor
ANKASYS supported TÜBİTAK BİLGEM with ASIC design, verification and RTL-to-GDS engineering for the RISC-V based ÇAKIL microprocessor.
Read story →
ANKASYS Signed a Contract with Endress+Hauser Group
ANKASYS signed a contract with Endress+Hauser Group, extending its specialist engineering work into industrial measurement and instrumentation programs.
Read story →ANKASYS IN PRACTICE
Engineering, technical exchange and team life.
A few real photographs from the company archive — different from the images used on the technical pages.
TRAINING
Engineering knowledge transferred in structured programs.
ANKASYS offers technical trainings derived from hands-on design and verification experience.
VerilogDesign
SystemVerilogVerification
UVMMethodology
FPGASystem Design
DO-254Certification
ASICImplementation
BUILD WITH ANKASYS
Need specialist silicon, verification or GNSS engineering?
Talk to ANKASYS about ASIC/FPGA development, verification, physical implementation, GNSS receiver technology or IP licensing.
Start a conversation →