Receiver target
Define the intended GNSS receiver architecture and hardware target.
LICENSABLE GNSS IP
Correlator technology,
ready for integration.
Multi-constellation GNSS correlator IP for hardware-based receivers, with flexible sampling/IF configurations and FPGA-independent, ASIC-compatible implementation.
PRODUCT POSITIONING
A reusable digital correlator core with a clear integration boundary.
The public IP boundary is intentionally simple: digitized I/Q enters a reusable digital correlator core, and its outputs are integrated into the customer receiver architecture. Sampling and IF configuration, FPGA/ASIC target and program-specific customization are handled as part of the integration discussion.
PUBLIC INTEGRATION VIEWGNSS CORRELATOR IP
UPSTREAMRF Front-End + ADCExternal / customer receiver architecture
→
INPUTDigitized I/QConfigurable sample / IF context
→
ANKASYS LICENSABLE IP
Digital Correlator Core
→
Channel 01Channel 02Channel …Channel N
Reusable · Scalable · Multi-constellation
OUTPUT BOUNDARYCorrelation / Timing InterfaceReceiver tracking, PPS and system processing context
FPGA FAMILY INDEPENDENTASIC COMPATIBLECUSTOMIZABLE IMPLEMENTATION
This diagram intentionally shows the public IP boundary at integration level; customer-specific receiver implementation details are not exposed.
01Six-constellation architectureReusable correlator architecture supporting GPS, Galileo, BeiDou, GLONASS, QZSS and NavIC receiver implementations.
02Multi-band L1 + L2 + L5Supports receiver processing and configurable sampling/IF integration across L1, L2 and L5 bands.
03FPGA agnostic / ASIC readyNo dependence on vendor-specific FPGA resources; suitable for ASIC implementation.
04No separate CPU/DSP IP licenseNo additional third-party processor or DSP IP license is required for the ANKASYS receiver solution.
05CustomizableCan be adapted to customer requirements, including low-power oriented implementations.
06Validated & deliveredTested with synthetic laboratory data and real-world signals; already delivered to customers.
07Receiver-level servicesIntegration scope can include RTK, EGNOS, Galileo OSNMA and HAS, dead reckoning and low-jitter PPS.
08Integration supportBacked by ANKASYS FPGA, ASIC and complete receiver engineering capability.
RECEIVER CHAIN CONTEXT
Correlator IP sits inside a real receiver architecture.
The digital correlator interfaces with sampled data coming from the RF front-end and ADC path. These photographs show ANKASYS-owned GNSS receiver hardware and prototype boards used in the broader receiver engineering context.
ENGAGEMENT
Start with the target receiver, not a generic datasheet.
The public product description focuses on integration-relevant capabilities without exposing customer-specific implementation details. A technical discussion can align sampling and IF configuration, target FPGA or ASIC, customization requirements, power goals and receiver integration scope.
Integration context
Align the correlator boundary with the surrounding digital baseband and receiver processing.
Technical scope
Review the relevant implementation and integration details for the program.
Licensing path
Agree the appropriate IP licensing and engineering-support model.
FAQ
Useful first questions.
Is this tied to a specific FPGA family?
No. The IP is designed without dependence on vendor-specific FPGA resources and can be mapped to different FPGA families. The same architecture is suitable for ASIC implementation.
Do we need to license a separate CPU or DSP IP?
No additional third-party CPU or DSP IP license is required for the ANKASYS GNSS receiver solution. ANKASYS can discuss the complete receiver integration context around the correlator IP.
Can the IP be customized?
Yes. The implementation can be adapted to customer requirements; low-power oriented customization is one example of the available engineering scope.
Has the technology been tested outside simulation?
Yes. It has been tested with synthetic laboratory data and with real-world GNSS signals, and the technology has already been delivered to customers.
What timing output is available?
The receiver architecture supports a low-jitter PPS (pulse-per-second) output for timing-oriented applications.
How do we start a licensing discussion?
Send us the target receiver context, intended FPGA or ASIC platform, sampling/IF requirements and any customization goals you want to discuss.
Planning a GNSS receiver?
Discuss correlator IP licensing, receiver architecture and FPGA/ASIC integration with ANKASYS.